Analysis of Low Power 1-bit Adder Cells Using Different XOR-XNOR Gates

摘要

Addition is the basic arithmetic operation used in many VLSI circuits. Reduction in power dissipation of 1 bit adder cell will improve the performance of most of electronic devices. In this paper, 1 bit adder cells were analyzed with respect to supply voltage, temperature, width and length variation of all transistors in circuits. The 1 bit adders were designed using 10, 8 and 6 transistors using different equations of sum and carry. The adder designs considered in this paper are SERF adder, 13A adder, CLRCL adder, 8T adder and 6T adder. The comparison was done with respect to power, delay and area. The adder designs were checked for their robustness by varying supply voltage and temperature. The simulations were carried using OrCAD PSpice in 180nm technology with 1.8V supply voltage. Simulation results showed that SERF adder has lowest power dissipation of all adders. Delay of Sum signal was lowest in CLRCL adder and delay of Carry signal was lowest in 13A adder. The 6T adder was found to be best when area was considered as it is designed using less number of transistors as compared to all other adder designs. The adder designs can be chosen according to our design considerations.