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Stress Distribution of Stacked Chip Package in Curing Process

机译:固化过程中堆叠式芯片封装的应力分布

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In this paper, packaging process for a typical stacked three-chip packaging structure has been studied in detail by finite element analysis (FEA) method. The simulation shows that thermal stress may result in die crack and delaminafion before package has been finished. During the each curing process, the stresses of joints of die in the bottom layer are largest and the system reliability is not lowered over three layers die. The package would be destroyed most easily in cure Ⅱ step. Failure rate of upper die is also high in the cure Ⅲ, as the Epoxy Molding Compound (EMC) can bring residual stress of phase changing, and combining FEA results, the package structure has been optimized.
机译:在本文中,通过有限元分析(FEA)方法详细研究了典型的堆叠三芯片封装结构的封装工艺。仿真表明,热应力可能会在封装完成之前导致芯片开裂和脱层。在每个固化过程中,最底层的模具接缝应力最大,并且在三层模具上系统可靠性不会降低。在固化Ⅱ步骤中,包装最容易被破坏。在固化Ⅲ中,上模的故障率也很高,因为环氧模塑化合物(EMC)可以带来相变的残余应力,并结合有限元分析结果,对封装结构进行了优化。

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