Challenges in Developing CMP Processes: STI and Copper/Low-k Polishing and Post CMP Cleaning

摘要

Since its invention by IBM in the early 1980s, Chemical Mechanical Planarization (CMP) has enabled the semiconductor industry to achieve smaller geometries for vias, contacts and metal line widths, resulting in higher density chips for logic and memory devices. Yet CMP continues to face many new challenges due to the introduction of new materials or more exacting polishing requirements. As feature sizes continue to shrink, there will also be tighter constraints on scratches and particles. Several new approaches to CMP are currently being explored by the semiconductor industry to address these challenges, including new STI and copper/low-k slurries and more effective post CMP cleaning. Other areas include fixed abrasive planarization, abrasive-free slurries and point-of-use blending. Another challenge is DI water consumption by the semiconductor industry. A typical fab consumes 240 million gallons of water for both BEOL and FEOL processes (～1500 gals/200 mm wafer) and the CMP process accounts for about 5-9% of the total water. There is the critical need to eliminate particle and metal ion contamination during post CMP, while attempting to reduce water usage levels.