STRUCTURE OF STATE MACHINE FOR GENERATING HALF-FULL FLAG AND HALF-EMPTY FLAG IN A SYNCHRONOUS FIFO

摘要

PROBLEM TO BE SOLVED: To provide a state machine for generating a half-full flag for use in combination with non-synchronous FIFO(First-In First-OUT). ;SOLUTION: The state machine to be used for remarkably shortening the delay of flag generation is constituted. Moreover, MTBF(Mean Time Between Failures) is very much extended. In this method, a pair of state variables P', Q', S' indicating the next state is generated by three state variables P, Q, S indicating the preceding state and the other three inputs (WRH of logical OR of the read half-full flag RH and write half-full flag WH, external write clock input W and external read clock input R). The next state variables P', Q', S' are particularly generated by a product of the preceding state variables P, Q, S, a complement signal of the preceding state variable and signal WRH. This half-full flag is generated using the digital logic decoding technology for controlling an input from the next three state variables, read clock signal and write clock signal.;COPYRIGHT: (C)1997,JPO