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Method for minimizing lateral and vertical dopant diffusion in gate structures
Method for minimizing lateral and vertical dopant diffusion in gate structures
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机译:最小化栅极结构中横向和垂直掺杂剂扩散的方法
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摘要
Methods and apparatus for to methods and apparatus for fabricating gate structures, which include barrier layers, within an integrated circuit are disclosed. According to one aspect of the present invention, a method for minimizing dopant outdiffusion within an integrated circuit involves forming a gate oxide 208 layer over a substrate 206, and forming a layered silicon structure 210 over the gate oxide layer. A silicide layer 214 is formed atop the layered silicon structure. In one embodiment, forming a layered silicon structure includes depositing a first doped silicon layer over the gate oxide layer, forming a first oxide layer over the first silicon layer, nitridizing the first oxide layer, and etching the nitridized first oxide layer to expose nitride at a grain boundaries of the first silicon layer. A second silicon layer may then be deposited over the nitride exposed at the grain boundaries of the first silicon layer. In such an embodiment, nitridizing the first oxide layer causes nitrogen to be diffused into at least a portion of the first doped silicon layer.
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