High voltage generating circuit for charge pump of e.g. flash EEPROM memory

摘要

The circuit has a memory cell array, a row decoder, column decoder, and a Y-access portion for operating the cell array. A clock generates two signals (CLK1,1a) during read and standby mode and program and ensure mode. A first pump outputs a constant high voltage from the first clock signal during read and standby (RVPGG) or pumping voltages during program and erasure modes, where second and third clock generators signal to a second pump, producing a third voltage. A third pump driven by clock three produces a fourth pump voltage.