Nonvolatile semiconductor memory device having row decoder

摘要

A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N- channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during other modes.