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SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
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机译:用于并行处理器体系结构的SRAM控制器以及使用读取和读取/写入队列控制对RAM的访问的方法
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摘要
A controller for a random access memory (RAM), such as a static ram (SRAM), includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues. The memory controller may be used in parallel processing systems and may also include an order queue, a lock lookup content addressable memory (CAM) and a read lock fail queue. A system including a media access controller (MAC), a network processor and an SRAM controller, and a method for controlling a RAM, are also described.
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