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Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
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机译:用于并行处理器体系结构的Sram控制器,包括读取队列和用于处理请求的订单队列
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摘要
A controller for a random access memory includes an address and command queue that holds memory references from a plurality of microcontrol functional units. The address and command queue includes a read queue that stores read memory references. The controller also includes a first read/write queue that holds memory references from a core processor and control logic including an arbiter that detects the fullness of each of the queues and a status of completion of outstanding memory references to select a memory reference from one of the queues.
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