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Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity
Fabrication method of self-aligned ferroelectric gate transistor using buffer layer of high etching selectivity
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机译:利用高刻蚀选择性的缓冲层制备自对准铁电栅晶体管的方法
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摘要
A fabrication method of a self-aligned ferroelectric gate transistor using a buffer layer of high etching selectivity is disclosed. A stacked structure is formed with a buffer layer with high etching selectivity inserted between a silicon substrate and a ferroelectric layer, and etching is performed on a portion where a source and a drain will be formed and then stopped at the buffer layer, thereby fabricating a self-aligned ferroelectric gate transistor without damage to the silicon thin film, and thus, an integration degree of a chip can be improved.
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