METHOD FOR FABRICATING SELF-ALIGNED FERROELECTRIC GATE TRANSISTOR USING BUFFER LAYER WITH HIGH ETCH SELECTIVITY TO INCREASE INTEGRATION OF SELF-ALIGNED FERROELECTRIC GATE TRANSISTOR WHILE PREVENTING SILICON SUBSTRATE FROM BEING DAMAGED

摘要

PURPOSE: A method for fabricating a self-aligned ferroelectric gate transistor using a buffer layer with high etch selectivity is provided to increase integration of a self-aligned ferroelectric gate transistor while preventing a silicon substrate from being damaged by performing a dry etch process after a buffer layer with high etch selectivity is interposed between the silicon substrate and a ferroelectric layer. CONSTITUTION: A buffer layer(2) made of a material with high etch selectivity is formed on a silicon substrate(1). A ferroelectric layer and an upper electrode are formed on the buffer layer. The ferroelectric layer and the upper electrode except a portion corresponding to a gate(5) are etched. An etch process stops in the buffer layer. A source/drain is formed in a portion etched by an ion implantation process.