首页> 外国专利> FORMING METHOD OF GATE ELECTRODE USING RECESS REGION IN CONDUCTIVE LAYER FOR FORMING GATE ELECTRODE AND DIELECTRIC SPACER AT SIDE WALL OF RECESS REGION

FORMING METHOD OF GATE ELECTRODE USING RECESS REGION IN CONDUCTIVE LAYER FOR FORMING GATE ELECTRODE AND DIELECTRIC SPACER AT SIDE WALL OF RECESS REGION

机译:在导电区侧壁上形成导电层和栅电极的导电层中使用导电区的导电层形成栅极的方法

摘要

Purpose: a method of forming of a gate electrode is arranged to reduce notch defect, to obtain there is a gate electrode of a smooth profile to use a recess region in a conductor layer, it is used to form a gate electrode and a dielectric spacer in the side wall of recess region, before the formation for completing gate electrode. Construction: a gate insulating layer (20) is formed in semi-conductive substrate (10). One conductor layer (30) is formed in gate insulating layer. One, which covers capacitor pattern (41), is formed in conductor layer. By using capacitor pattern is covered as a mask, the part of conductor layer is etched, and forms a recess region (31) in conductor layer. One dielectric spacer (51) is formed in the side wall of recess region. By using capacitor pattern and dielectric spacer is covered as a mask, remaining conductor layer is etched, to make gate insulating layer expose and form gate electrode.
机译:目的:布置栅电极的形成方法以减少切口缺陷,以获得具有光滑轮廓的栅电极以在导体层中使用凹陷区域,该方法用于形成栅电极和电介质隔离物在凹陷区域的侧壁中,在完成栅极电极的形成之前。构造:在半导体衬底(10)中形成栅极绝缘层(20)。在栅极绝缘层中形成一个导体层(30)。覆盖电容器图案(41)的一个形成在导体层中。通过使用电容器图案作为掩模被覆盖,导体层的一部分被蚀刻,并且在导体层中形成凹陷区域(31)。在凹部区域的侧壁上形成有一个电介质隔离物(51)。通过使用电容器图案并覆盖电介质间隔物作为掩模,蚀刻剩余的导体层,以使栅绝缘层暴露并形成栅电极。

著录项

  • 公开/公告号KR20040105153A

    专利类型

  • 公开/公告日2004-12-14

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20030036442

  • 发明设计人 KIM SEONG JIN;JU JUN YONG;

    申请日2003-06-05

  • 分类号H01L21/336;

  • 国家 KR

  • 入库时间 2022-08-21 22:06:22

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号