Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device

摘要

A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.