WAFER LEVEL CHIP ON CHIP PACKAGE WITH A REDUCED MOUNTING HEIGHT AND IMPROVED SOLDER BONDING RELIABILITY, A CHIP ON PACKAGE, AND A MANUFACTURING METHOD THEREOF, CAPABLE OF MOUNTING A PLURALITY OF SEMICONDUCTOR CHIPS ON ONE PACKAGE WITH A CHIP ON CHIP METHOD

摘要

PURPOSE: A wafer level chip on chip package with a reduced mounting height and improved solder bonding reliability, a chip on package, and a manufacturing method thereof are provided to minimize a semiconductor chip mounting area by changing a horizontal arrangement state into a vertical arrangement state.;CONSTITUTION: A pair of packages(300,400) with different functions are manufactured. The pair of packages are vertically stacked. One of the pair of the packages is comprised of a memory semiconductor chip package with a memory function. The other of the pair of the packages is comprised of a logic semiconductor chip package with a logic function.;COPYRIGHT KIPO 2010