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VERTICAL STRUCTURE OF A NON-VOLATILE MEMORY DEVICE, CAPABLE OF IMPROVING THE CONTROLLING RELIABILITY OF STRING-SELECTION TRANSISTORS, MEMORY CELLS, AND GROUND-SELECTION TRANSISTORS
VERTICAL STRUCTURE OF A NON-VOLATILE MEMORY DEVICE, CAPABLE OF IMPROVING THE CONTROLLING RELIABILITY OF STRING-SELECTION TRANSISTORS, MEMORY CELLS, AND GROUND-SELECTION TRANSISTORS
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机译:非挥发性存储设备的垂直结构,能够提高选弦晶体管,存储单元和接地选择晶体管的控制可靠性
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摘要
PURPOSE: The vertical structure of a non-volatile memory device is provided to reduce the length of the gate of ground-selection gate electrodes by forming two or more string-selection transistors.;CONSTITUTION: A semiconductor pillar is vertically expanded to the upper side of a substrate. A NAND string(NS) is vertically expanded to the upper side of the substrate along the sidewall of the semiconductor pillar. The NAND string includes first selection transistors(TG1, TG2) which are adjacently arranged on one side of plurality of memory cells(MC). A plurality of word-lines(WL0 to WLn) is combined to a plurality of memory cells of the NAND string. A first selection line is commonly combined to the first selection transistors of the NAND string.;COPYRIGHT KIPO 2010
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