An integrated circuit with a memory having a plurality of memory cells with synchronous construction, the yield with clock missing units are connected, as well as a method of designing such a circuit

摘要

An integrated circuit (200) with:a clock source, which is formed to provide a clock signal;a plurality of clock yield missing units (240), each of which is connected to the clock signal and a control signal is to be received, wherein the plurality of clock yield missing units (240) are formed, the clock signal when the control signal is in a set state; anda memory area (210) having memory cells, which often divided into a plurality of groups, each frequently as a function of the group of memory cells of a predetermined different access frequency during a specified operating mode, and the clock signal from a corresponding of said plurality of clock yield missing units (240) receives.