8GHz clocking circuits for a 16Gb/s/pin asymmetric memory interface [1] are described. A combination of an LC-PLL and a ring-PLL achieves improved jitter performance for multiple phase outputs with a wide frequency range. A direct phase mixer and a digitally controlled duty-cycle corrector (DCC) are time-multiplexed between transmitter (TX) and receiver (RX), thereby reducing area and power. The prototype chip implemented in a 65nm CMOS technology has measured 734fs RJ (rms) at the TX output when operating at 16Gb/s.
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机译：描述了用于16GB / S /引脚不对称存储器接口[1]的8GHz时钟电路。 LC-PLL和Ring-PLL的组合实现了具有宽频范围的多相输出的改进的抖动性能。直接相混频器和数字控制的占空比校正器（DCC）在发射器（TX）和接收器（RX）之间是时间复用的，从而减少了区域和功率。在65nm CMOS技术中实现的原型芯片在16GB / s操作时在TX输出处测量了734FS RJ（RMS）。
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