INTEGRATED CIRCUIT HAVING A MEMORY WITH A PLURALITY OF STORAGE CELLS OF SYNCHRONOUS DESIGN AND CONNECTED TO CLOCK GATING UNITS

摘要

In a memory area having portions of predictable access frequency, such as in a memory area of a real time clock unit, a synchronous design may be implemented by associating storage cells of identical access frequency with a clock gating mechanism, thereby reducing power consumption. Hence, the synchronous design of the real time clock unit may provide reduced implementation effort and enhanced verification capability.