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Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies
Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies
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机译:应用高压轻掺杂漏极(LDD)CMOS技术的静电放电(ESD)保护
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摘要
An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration.
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