METHOD FOR CONTROLLING A THRESHOLD VOLTAGE OF A GATE LAMINATE OF A PMOS DEVICE INCLUDING A GST CONTROL LAYER ON A GATE ELECTRODE METAL

摘要

PURPOSE: A method for controlling a threshold voltage of a gate laminate of a PMOS device is provided to easily control a threshold voltage of a gate laminate by doping a high-k gate dielectric layer.;CONSTITUTION: A gate dielectric layer is a metal oxide or semi-metal oxide with a first electronegativity and is formed on a semiconductor substrate. A dielectric threshold voltage control layer is a metal oxide or semi-oxide with a second electronegativity. A gate electrode is formed on the gate dielectric layer and the threshold voltage control layer. An effective work function of the gate laminate is controlled by controlling the thickness and composition of a dielectric threshold voltage control layer. A second electronegativeity is higher than the first electronegativity and the electronegativity of Al2O3.;COPYRIGHT KIPO 2011