首页> 外国专利> METHOD FOR FORMING SPLIT GATE ELECTRODE OF NVM DEVICE TO MAKE GATE OXIDE LAYER UNDER CONTROL GATE OF SPLIT GATE ELECTRODE HAVE WITHSTAND VOLTAGE WITH RESPECT TO HIGH VOLTAGE APPLIED TO CONTROL GATE AND MAKE OXIDE LAYER IN CONTACT WITH CONTROL GATE SIDEWALL SMOOTHEN TUNNELING EFFECT OF ELECTRONS

METHOD FOR FORMING SPLIT GATE ELECTRODE OF NVM DEVICE TO MAKE GATE OXIDE LAYER UNDER CONTROL GATE OF SPLIT GATE ELECTRODE HAVE WITHSTAND VOLTAGE WITH RESPECT TO HIGH VOLTAGE APPLIED TO CONTROL GATE AND MAKE OXIDE LAYER IN CONTACT WITH CONTROL GATE SIDEWALL SMOOTHEN TUNNELING EFFECT OF ELECTRONS

机译:形成NVM器件的分栅电极以在分栅电极的控制栅下具有相对于高电压的栅氧化物层的方法,用于控制栅,并使氧化层与控制栅的侧壁接触。

摘要

Purpose: a kind of method is used to form under a control door of the gate electrode that a gate electrode device to split of a NVM (nonvolatile memory) splits one and is arranged to manufacture a gate oxide and has the one of the high voltage for being applied to control door relative to one to be subjected to voltage and with a control door side wall contact manufacture oxide layer by making oxide skin(coating) be present between control door and a floating gate tunnel-effect of smooth electronics and under control door with different thicknesses. Construction: after the nitride layer, white layer mode for selectively exposing a polysilicon layer is formed, the spacer oxide layer with a uniform thickness is formed. One etch-back process will carry out forming a gasket, and a polysilicon layer mode split and a power supply line are formed in the opening of nitride layer, white layer mode. After the polysilicon layer mode of exposed nitride layer, white layer mode and exposure is etched to form the floating gate that one splits, gate oxide, which is present in the floating gate to split other than a region and is etched away to an once substrate (100), to be not exposed. The second gate oxide with a uniform thickness is formed in composite structure.
机译:目的:一种用于在栅电极的控制门下形成一种方法,该方法是将要分裂的NVM(非易失性存储器)的栅电极器件分裂成一个并布置成制造栅氧化物并具有高电压之一用于控制门相对于要施加电压的控制门,并通过在控制门和平滑电子器件之间的控制门与浮栅隧穿效应之间存在氧化物表皮(涂层)而与控制门侧壁接触以制造氧化物层不同厚度的门。构造:在氮化物层之后,形成用于选择性地暴露多晶硅层的白层模式,从而形成具有均匀厚度的隔离氧化物层。将执行一种回蚀工艺以形成垫片,并且在氮化物层(白色层模式)的开口中形成多晶硅层模式分裂和电源线。在暴露的氮化物层的多晶硅层模式,白色层模式和暴露之后,被蚀刻以形成一个被分裂的浮栅,存在于该浮栅中的硅氧化物将分裂成一个区域以外的其他区域,并被蚀刻掉成一次衬底。 (100),不要暴露。具有均匀厚度的第二栅极氧化物以复合结构形成。

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