In order the digital phase simulation looping (DPLL) the time anti- digital converter (TDC) the system and the mannered null phase simulation looping in order to calibrate the power

摘要

Although the digital phase synchronous loop (DPLL) the time anti- digital transmitter (TDC) the power on gating window is calibrated, the system and the method of being related are disclosed. The gating window while operating TDC simultaneously with efficient method of electric power, is calibrated in order to guarantee the appropriate operation of DPLL. Especially, the technology sets width of the TDC gating window to established value; Until the control loop is locked substantially, operate DPLL; While monitoring the phase error signal which is formed by the phase error device of DPLL, just the specified quantity makes the width of the TDC gating window decrease; When phase error arrives substantially in specified threshold, or crossing decide the present width of the TDC gating window; And just the specified quantity which is installed in the margin of error of operational width of the TDC gating window requires the fact that it increases the present width of the TDC gating window.