digital phase locked loop time (DPLL) - Power to-digital converter (TDC) - On the gating window The systems and methods relating to the correction that is disclosed. Gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique is to set the width of the TDC gating window to a default value; Control loop is operating the DPLL until substantially locked; While monitoring the phase error signal generated by the phase error device of a DPLL, to reduce the width of the TDC gating window by a predetermined amount; The phase error is to determine the current width of the TDC gating window when it reaches the predetermined threshold or cross a predetermined threshold substantially; And TDC gating involves increasing the width of the current of the TDC gating window to establish a margin of error of the operation of the window width by a predetermined amount.
展开▼