Analysis and Design of a Time-to-Digital Converter-Based Digital Phase Locked Loop

摘要

Multi gigabit per second serial binary links are used to implement cross chip communication because of the limited number of I/O pins on a system on a chip package and wireline interconnections on a printed circuit board. Scaling of microprocessors used in mobile phones, tablets and high performance main frame machines used in large scale data centers has become possible due to developments in wireline communications. This thesis presents an analysis and design of a high speed, low power and low jitter digital phase locked loop (PLL), to be used in high speed wireline communications. The methodology used was to design and validate an analog PLL, followed by a digital PLL, by replacing the analog components with their digital counterparts. The phase frequency detector, analog loop filter, and a voltage controlled oscillator in an analog PLL were replaced by a high resolution time-to-digital converter (TDC), a behavioral digital loop filter and a low phase noise LC cross coupled voltage controlled oscillator (VCO), respectively. Finally achieved design parameters include, a clock frequency of 5 GHz, a power dissipation of 750 microW, a timing jitter of 3.32 ps and a VCO phase noise of -108 dBc/Hz at 1 MHz frequency offset. It was concluded that a vernier delay line TDC with a timing resolution of 10 ps can be used in place of a conventional phase detector, to design a high speed, low power and low timing jitter digital phase locked loop.