A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution.

摘要

As the scale of Integrated Circuit (IC) continues to shrink, unlike digital circuits, design of analog circuits has been more difficult due to unfavorable changes from the device scaling such as reduced supply voltage, low transistor output resistance and high leakage current. Recently there has been efforts to replace the hard-to-design analog circuits with digital circuits without performance degradation. As an example, a charge-pump phase-locked loops (PLLs) is replaced by a digital PLL. This technical transition is achieved in deep-submicron CMOS process by utilizing a time-to-digital converter (TDC), which quantizes time intervals between two edges and a digitally-controlled oscillator (DCO), of which frequency is controlled by digital words instead of voltage.;The first part of this dissertation is about the realization of a coarse-fine time-to-digital converter (TDC) that amplifies a time residue to improve time resolution, adapting the idea from a coarse-fine analog-to-digital converter (ADC). A new digital circuit has been developed to amplify the time difference with a higher gain (>16) and larger range (>80ps) than existing solutions do. Although we have developed the improved TA, direct adaptation of the conventional coarse-fine ADC architecture is not an appropriate solution for TDCs: input time can not be stored and the gain of a time amplifier (TA) can not be controlled precisely. A new coarse-fine TDC architecture is proposed by using an array of time amplifiers and two identical fine TDCs that compensate the variation of the TA gain during the conversion process. The measured DNL and INL are +0.8 LSB and +/-3 LSB, respectively, with a value of 1.25ps per 1LSB, while the standard deviation of output code for constant inputs remains below 1LSB across the TDC range. Although the nonlinearity is larger than 1 LSB, using an INL lookup table or better matched delays in the coarse TDC delay chain will improve the linearity further.;The second part of the dissertation presents a digital phase; locked loop (DPLL) which is designed as part of a flexible RF transmitter [1]. The DPLL is designed to have wide bandwidth and low noise, based on a new time-to-digital converter with subpicosecond resolution. The TDC utilizes a coarse-fine architecture that amplifies a time residue. A spur reduction technique in a counter-assisted DPLL is also presented. The loop bandwidth is set to 400kHz with a 25MHz reference targeted for GSM. The in-band phase noise contribution from the TDC is 116dBc/Hz; this is equivalent to 1ps rms quantization noise. The phase noise at high-band 400kHz offset is -117 dBc/Hz, and the integrated rms phase error is 0.3°.