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REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS
REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS
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机译:降低3D封装集成电路的模片到模片粘接期间静电放电损坏的可能性
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摘要
Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.
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