首页> 外国专利> REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS

REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS

机译:降低3D封装集成电路的模片到模片粘接期间静电放电损坏的可能性

摘要

Mitigating electrostatic discharge damage when fabricating a 3-D integrated circuit package, wherein in one embodiment when a second tier die is placed in contact with a first tier die, conductive bumps near the perimeter of the second tier die that are electrically coupled to the substrate of the second tier die make contact with corresponding conductive bumps on the first tier die that are electrically coupled to the substrate of first tier die before other signal conductive bumps and power conductive bumps on the second tier and first tier dice make electrical contact.
机译:在制造3-D集成电路封装时,减轻静电放电损坏,其中在一个实施例中,当第二层裸芯放置与第一层裸芯接触时,第二层裸芯的周边附近的导电凸块电耦合到衬底在第二层和第一层管芯上的其他信号导电凸块和功率导电凸块进行电接触之前,第二层管芯的第一凸块与第一层管芯上的相应的导电凸块接触,该导电凸块与第一层裸片的衬底电耦合。

著录项

  • 公开/公告号IN2012MN02197A

    专利类型

  • 公开/公告日2014-03-28

    原文格式PDF

  • 申请/专利权人

    申请/专利号IN2197/MUMNP/2012

  • 申请日2012-09-17

  • 分类号H01L21/70;H01L23/538;

  • 国家 IN

  • 入库时间 2022-08-21 15:57:34

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号