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REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS
REDUCING SUSCEPTIBILITY TO ELECTROSTATIC DISCHARGE DAMAGE DURING DIE-TO-DIE BONDING FOR 3-D PACKAGED INTEGRATED CIRCUITS
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机译:降低3D封装集成电路的模片到模片粘接期间静电放电损坏的可能性
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摘要
This invention relates to mitigate the risk of electrostatic discharge when producing a 3-D integrated circuit package , in one embodiment , when the second -tier die is configured to contact the first -tier die , near the perimeter of the electrically conductive bumps coupled to second tier die to the substrate of the second tier dies , and the second tier other signals on the first -tier conductive bump dies and power conductive bumps before achieving an electrical contact and forms a corresponding conductive bumps with contact on the first tier die is electrically coupled to the substrate of the first -tier ring die .
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