Brief description of embodiments of a device for the transistors are constrained by siliciding of the source and drain regions

摘要

The method involves forming a barrier layer (130) containing a material on semiconductor areas (125, 126) located on both sides of a gate block of a transistor e.g. P-channel metal oxide semiconductor. Openings (141, 143, 145, 147) traversing the layer are formed. A metallic material is deposited via the openings, followed by annealing so as to form metal alloy and semiconductor areas i.e. silicide areas, where volume of the metallic material and annealing duration are selected so as to form two of the silicide areas exerting compressive stress on a channel area of the transistor. An independent claim is also included for a microelectronic device with transistors.