Semiconductor integrated circuit of the test pattern generation method and semiconductor integrated circuit of the test pattern generator, control program, readable recording medium

摘要

PROBLEM TO BE SOLVED: To surely apply a predetermined voltage between terminals in all transistors for composing a cell during a predetermined time, and improve a transistor activation rate without inspecting a logical value e.g. a toggle rate such as a wiring voltage between the cells.;SOLUTION: A CPU 1 uses a transistor activity condition table for indicating the existence of the activation of the transistor corresponding to a voltage between the terminals of the transistors within the cell and a voltage at an input/output terminal per cell type of the cell for constituting a semiconductor integrated circuit, selects terminals of the transistors between which a voltage of a predetermined value or higher is applied, assigns a cell state as an input value to the cell having the transistor so as to apply the predetermined voltage between the terminals of the transistor, and generates a test pattern as an input sequence to an external input terminal of the cell so as to achieve the cell state based on a test pattern generation program as a control program of a HDD 2.;COPYRIGHT: (C)2010,JPO&INPIT