Fantestic: towards a powerful fault analysis and test pattern generator for integrated circuits

摘要

A methodology relating physical defects to the circuit-level faulty behavior caused by these defects and a fast algebraic implementation to provide a realistic fault list are proposed. In conjunction with the obtained statistical data on the likelihood of each fault and the knowledge of its best observable electrical manifestation, a solid basis for an effective and powerful test pattern generation is provided. To achieve an accurate modeling of bridging faults, a novel fault model, the large-scope short, is developed and implemented. In contrast to other fault analysis procedures which use time-consuming simulation methods to generate or induce physical defects, the proposed Fantestic methodology is very fast in extracting defects and converting them to a ranked fault list. The analysis of some sample CMOS circuits illustrates the effect of different physical defects on circuit-level faults.