Paralleled Drive Devices Per Bitline in Phase-Change Memory Array

摘要

Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size.