A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

摘要

A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.