A 7F2 cell and bitline architecture featuring tiltedarray devices and penalty-free vertical BL twists for 4-Gb DRAMs

摘要

A 7F2 DRAM trench cell and corresponding verticallynfolded bitline (BL) architecture has been fabricated using a 0.175 Μmntechnology. This concept features an advanced 30° tilted arrayndevice layout and an area penalty-free inter-BL twist. The presentednscheme minimizes local well noise by maximizing the number of twistingnintervals. A significant improvement of signal margin was measured on an32-Mbyte test chip