DRAM cell field architecture with superposed bitline switches and bitlines

摘要

The invention relates to a DRAM cell field architecture, in which, in each individual memory block, bit switches (5 to 12) are used to select in each case from a plurality of bit line pairs one bit line pair (BLj, BLj+2), and of the bit line pairs respectively selected in each memory block in turn only the bit line pairs of the selected memory block are switched through to the superposed bit lines (IOk to IOk+3). The superposed bit lines may in this case run together with the superposed bit switch lines (CSLk to CSLk+3), driving the bit switches, on a single, for example the second, metallisation level, thereby better utilising the said level. Due to the invention, depending on the required degree of parallelism, it is possible to save interpreters on account of the superposed bit lines, retaining the advantage in individual access of a short access time with moderate power consumption. IMAGE