Architectures for terabit cell switches supporting differentiated quality of service.

摘要

Architectures for very-high-speed switching of fixed-size packets, or “cells” are presented and analyzed by simulation. Each architecture is designed to schedule cells in earliest-deadline-first (EDF) order. EDF ordering can be used with fair queueing as well as arbitrary traffic schedulers to deliver differentiated service. An initial distributed-queue architecture for 2 x 2 full-duplex 10Gb/s switching is discussed, and a custom circuit design is detailed. Due to limitations in scaling to terabit rates, an input queued configuration is adopted. A non-blocking crossbar is incorporated, which can support 32 full-duplex 40Gb/s ports with aggregate capacity of 1.28Tb/s full-duplex. As a first-cut, queues are grouped by output in an effort to optimize scheduling, which ideally should be an independent function at each output of the mix of traffic exiting said output. While conceptually elegant, the grouping is found to be sub-optimal because wiring complexity prevents sufficient information exchange between input buffers and output ports. The fundamental problem is that buffers are constrained to source and sink only one cell per cell-time. This is in contrast to the output queued switch architecture which requires the buffer to sink multiple cells per cell-time. The input queued configuration is able to operate at higher rates for a given memory bandwidth, but it is not simultaneously able to match the optimal scheduling characteristics of the output queued configuration.; A traditional input queued configuration is then adopted, foregoing the pretense of imitating output queued scheduling by virtue of queue grouping. A central arbiter is tasked with the scheduling of cells according to deadlines. The latency characteristics of this approach are compared to those of an ideal output queued switch, and the deviation is found to be modest for offered loads up to 95%. The implication of this finding is that input queued switches can be used at high operating load without significant compromise in scheduling. This is important because input queued switches can support much higher link rates for any given memory bandwidth.