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Scalable multi-module packet switches with quality of service.

机译:具有服务质量的可扩展多模块分组交换机。

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摘要

The rapid growth in packet-based network traffic has resulted in a growing demand for network switches that can scale in capacity with increasing interface transmission rates and higher port counts. Furthermore, the continuing migration of legacy circuit-switched services to a shared IP/MPLS packet-based network requires such network switches to provide an adequate Quality of Service (QoS) in terms of traffic prioritization, as well as bandwidth and delay guarantees. While technology advances, such as the usage of faster silicon and optical switching components, provide one dimension to address this demand, architectural improvements provide the other. This dissertation addresses the latter topic. Specifically, we address the subject of constructing and analyzing high-capacity QoS-capable packet switches using multiple lower-capacity modules.;Switches with the output-queueing (OQ) discipline, in theory, provide the best performance in terms of throughput as well as QoS, but do not scale in capacity with increasing rates and port counts. Input-queued (IQ) switches, on the other hand, scale better but require complex arbitration procedures, sometimes impractical, to achieve the same level of performance. We leverage the state-of-the-art in OQ and IQ switching systems and establish a new taxonomy for a class of three-stage packet switches, which we call Buffered Clos Switches. The taxonomy is created by augmenting existing switching elements with aggregation, pipelining and parallelization techniques. This offers a switch designer several alternatives, each driven by specific design and re-use constraints, to build a high-capacity switch composed of lower-capacity basic elements.;We also present a formal framework for optimal packet-switching performance, in order to uniformly characterize the capabilities of the switches in the class. The optimality is based on establishing functional equivalence of a given switch and its associated arbitration algorithms with a well-understood ideal switch. For the items in the above taxonomy, we demonstrate how some existing algorithms perform with respect to the optimality criteria, and then augment the state-of-the-art by presenting algorithms and analytical results for stricter equivalence with an ideal switch.
机译:基于数据包的网络流量的快速增长导致对网络交换机的需求不断增长,这些交换机可以随着接口传输速率的提高和端口数量的增加而扩展容量。此外,将传统的电路交换服务不断迁移到基于IP / MPLS数据包的共享网络需要这种网络交换机在流量优先级,带宽和延迟保证方面提供足够的服务质量(QoS)。尽管技术的进步(例如使用更快的硅和光交换组件)提供了一个解决方案,可以满足这一需求,但体系结构的改进则提供了另一个方面。本文针对后一个主题。具体来说,我们解决了使用多个低容量模块构建和分析具有大容量QoS功能的分组交换机的主题。从理论上说,具有输出排队(OQ)原则的交换机在吞吐量方面也提供了最佳性能作为QoS,但不会随着速率和端口数的增加而扩展容量。另一方面,输入排队(IQ)交换机可扩展性更好,但需要复杂的仲裁程序(有时不切实际)才能达到相同的性能水平。我们利用OQ和IQ交换系统中的最新技术,并为一类三级分组交换机建立了新的分类法,我们将其称为缓冲关闭交换机。通过使用聚合,流水线和并行化技术扩展现有交换元素来创建分类。这为交换机设计人员提供了多种选择,每种选择均受特定设计和重复使用约束的驱使,以构建由低容量基本元素组成的高容量交换机。我们还提出了一个用于优化数据包交换性能的正式框架,以便以统一表征该类中交换机的功能。最优性基于建立给定交换机的功能等效性及其相关的仲裁算法以及一个众所周知的理想交换机。对于上述分类法中的项目,我们将演示一些现有算法相对于最佳性标准的性能,然后通过提供算法和分析结果以更理想的等效性与理想开关相提并论,从而增强了最新技术。

著录项

  • 作者

    Krishnan, Santosh.;

  • 作者单位

    Columbia University.;

  • 授予单位 Columbia University.;
  • 学科 Engineering Electronics and Electrical.;Computer Science.
  • 学位 Ph.D.
  • 年度 2006
  • 页码 293 p.
  • 总页数 293
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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