A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs

摘要

A 7F/sup 2/ DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 /spl mu/m technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip.