首页> 外国专利> Method of manufacturing a device of the field effect transistor is implemented on an array of nanowires vertical, the device of the transistor, electronic device comprising such devices of the transistors, and processor comprising at least such an electronic device

Method of manufacturing a device of the field effect transistor is implemented on an array of nanowires vertical, the device of the transistor, electronic device comprising such devices of the transistors, and processor comprising at least such an electronic device

机译:在垂直的纳米线阵列上实现制造场效应晶体管的器件的方法,该晶体管的器件,包括该晶体管的这种器件的电子器件以及包括至少这种电子器件的处理器

摘要

A process for fabricating a field-effect transistor device (20) implemented on a network of vertical nanowires (24), includes: producing a source electrode (26) and a drain electrode (30) at each end of each nanowire (24) symmetrically relative to the gate electrode of each elementary transistor implemented on a nanowire; creating a gate electrode by depositing a layer (38) of conductive material around a layer (36) of dielectric material that surrounds a portion of each nanowire (24), a single conductive layer (38) being used for all of the nanowires and the thickness of the conductive layer corresponding to the gate length of the transistor device; and insulating each electrode with a planar layer (32, 34) of a dielectric material in order to form a nanoscale gate and in order to insulate the contacts of each elementary transistor between the gate and the source and the gate and the drain.
机译:一种在垂直纳米线(24)的网络上实施的场效应晶体管器件(20)的制造方法,包括:在每条纳米线(24)的各端对称地产生源电极(26)和漏电极(30)。相对于在纳米线上实现的每个基本晶体管的栅电极;通过在围绕每个纳米线(24)一部分的介电材料层(36)周围沉积一层导电材料(38)来创建栅电极,单个导电层(38)用于所有纳米线,并且导电层的厚度对应于晶体管器件的栅极长度;并用介电材料的平面层(32、34)使每个电极绝缘,以形成纳米级的栅极,并使栅极和源极之间以及栅极和漏极之间的每个基本晶体管的触点绝缘。

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