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Interconnection of several levels of a stack of supports for electronic components

机译：电子元器件支架堆叠的多个层次的互连

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摘要

Method for producing a microelectronic device formed from a stack of supports (W) each provided with one or more electronic components (C) and comprising a conductive structure (170, 470) formed from a first blind conductive via (171b, 472) and a second blind conductive via (171a, 473) with a greater height, the first via and the second via being connected together.

机译：用于制造微电子器件的方法，该微电子器件由一堆支撑体（W）形成，每个支撑体均设有一个或多个电子组件（C），并包括由第一盲导电通孔形成的导电结构（ 170、470 ）（ 171 b， 472 ）和第二个盲导电通孔（ 171 a， 473 ），并且第一个过孔和第二个过孔连接在一起。 展开▼

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公开/公告号US9312169B2

专利类型

公开/公告日2016-04-12

原文格式PDF

申请/专利权人 COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENE ALT;
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申请/专利号US201414454023

发明设计人 GABRIEL PARES;CHRISTOPHE BOUVIER;
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申请日2014-08-07

分类号H01L21/30;H01L21/768;H01L23/12;H01L23/52;H01L23/552;H01L25/065;H01L25/00;H01L23/00;H01L27/06;H01L23/538;

国家 US

入库时间 2022-08-21 14:32:50

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