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DESIGN AND IMPLEMENTATION OF SHIELDED CHANNEL DOUBLE GATE JUNCTIONLESS METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR LOW POWER AND HIGH PERFORMANCE
DESIGN AND IMPLEMENTATION OF SHIELDED CHANNEL DOUBLE GATE JUNCTIONLESS METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR LOW POWER AND HIGH PERFORMANCE
A Shielded channel double gate junctionless metal oxide semiconductor transistor is described. In one aspect, a transistor device comprises a semiconductor material. The semiconductor material comprises first, second and third portions. The first, second and third portions are doped with dopants of the same polarity and the same concentrations. The transistor device further comprises an electrode connected to the second portion. A current flows between the first and third portions when a voltage is applied to the electrode
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