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Power-metal oxide semiconductor transistor e.g. power-insulated gate bipolar transistor, for integrated circuit, has inversion channel characterized as channel region, formed in section of body region and arranged in one semiconductor layer
Power-metal oxide semiconductor transistor e.g. power-insulated gate bipolar transistor, for integrated circuit, has inversion channel characterized as channel region, formed in section of body region and arranged in one semiconductor layer
The transistor has a semiconductor body (100) with a body region (13) arranged between a source region (14) and a drift region (11). The body has a semiconductor layer (110) from silicon carbide and another semiconductor layer (120) from a semiconductor material with other band gap than silicon carbide. The body and source regions are arranged section-wise in the layer (120), where the drift region is section-wisely arranged in the layer (110). An inversion channel from silicon characterized as a channel region (15) is formed in a section of the body region and arranged in the layer (120). An independent claim is also included for a method of manufacturing a power-metal oxide semiconductor-transistor.
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