Chip with interdigital capacitor in split-gate flash technology and method for its production

摘要

An integrated chip (100, 200, 300, 400) comprising: a well region (104, 606) located within an upper surface (102u) of a semiconductor substrate (102); a plurality of top electrodes (112, 112a, 112b, 112c) disposed over the semiconductor substrate (102) at locations vertically separated from the semiconductor substrate (102) by a first dielectric layer (106, 502); one or more bottom electrodes (108) extending vertically from between the plurality of top electrodes (112, 112a, 112b, 112c) to locations embedded within the well zone (104, 606); and a charge trapping dielectric layer (204, 204 ', 902) disposed between the semiconductor substrate (102) and the one or more lower electrodes (108) and between the plurality of upper electrodes (112, 112a, 112b, 112c) and the one or the plurality of lower electrodes (108).