Interdigital capacitor in split-gate flash technology

摘要

The present disclosure relates to a substrate having test lead letters used to identify a test lead on an integrated chip while avoiding contamination of high-k metal gate processes, and a method of forming the same. In some embodiments, the substrate comprises a semiconductor substrate. A test lead letter structure is disposed over the semiconductor substrate and includes one or more trenches that extend vertically between an upper surface of the test letter structure and a lower surface of the test lead letter structure. The one or more trenches are disposed within the test lead letter structure to form an opening in the upper surface of the test lead structure having a shape of an alphanumeric character.