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MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER
MEMORY CELL WITH HIGH-K CHARGE TRAPPING LAYER
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机译:具有高K电荷陷阱层的存储单元
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摘要
A non-volatile storage device with memory cells having a high-k charge storage region, as well as methods of fabrication, is disclosed. The charge storage region has three or more layers of dielectric materials. At least one layer is a high-k material. The high-k layer(s) has a higher trap density as compared to Si3N4. High-k dielectrics in the charge storage region enhance capacitive coupling with the memory cell channel, which can improve memory cell current, program speed, and erase speed. The charge storage region has a high-low-high conduction band offset, which may improve data retention. The charge storage region has a low-high-low valence band offset, which may improve erase.
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机译:公开了一种具有具有高k电荷存储区的存储单元的非易失性存储设备及其制造方法。电荷存储区具有三层或更多层介电材料。至少一层是高k材料。与Si 3 N 4相比,高k层具有更高的陷阱密度。电荷存储区域中的高k电介质增强了与存储单元通道的电容耦合,从而可以提高存储单元电流,编程速度和擦除速度。电荷存储区具有高-低-高导带偏移,这可以改善数据保留。电荷存储区具有低-高-低价带偏移,这可以改善擦除。
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