Stack engineering of TANOS charge-trap flash memory cell using high-K ZrO_2 grown by ALD as charge trapping layer

摘要

ZrO_2 with a k value of 30 grown by atomic layer deposition has been integrated as charge trapping layer alternative to Si_3N_4 in TANOS-like memory capacitors, with Al_2O_3 as blocking Oxide, SiO_2 as tunnel Oxide and TaN metal gate. The fabricated device featuring 24 nm ZrO_2 exhibits efficient program and erase operations under Fowler-Nordheim tunneling when compared to a Si_3N_4 based reference device with similar EOT and fabricated under the same process conditions. The effect of stack thermal budget (900-1030 ℃ range) on memory performance and reliability is investigated and correlated with physical analyses. Finally, scaling ZrO_2 down to 14 nm allows program and erase at lower voltages, even if the trapping efficiency and retention of these device need further improvements for the integration of ZrO_2 in next generation charge trapping nonvolatile memories.