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Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
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机译:在集成电路中产生模拟衬底耦合效应的电子电路的方法
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摘要
The present invention relates to design and manufacture of integrated circuits and more particularly to electrical modelling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, the modelling of substrate coupling effects in these circuits.
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