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Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit

机译:在集成电路中产生模拟衬底耦合效应的电子电路的方法

摘要

The present invention relates to design and manufacture of integrated circuits and more particularly to electrical modelling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, the modelling of substrate coupling effects in these circuits.
机译:本发明涉及集成电路的设计和制造,尤其涉及将高压功率器件与低压控制逻辑块相结合的集成电路的电气建模,甚至更具体地涉及这些电路中的衬底耦合效应的建模。

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