Method for generating an electronic circuit for modeling the effects of substrate coupling in an integrated circuit

摘要

Method for generating an electrical circuit comprising at least one network of diodes, resistors and / or homounions, modeling the parasitic effects of a substrate of an integrated circuit comprising electronic devices, said circuit being defined by a set of arrangements of mask layers and a file of technological rules, the method comprising: * generating (13) a simplified 3D arrangement of said integrated circuit from the set of mask layer arrangements and the file of technological rules only through the use of layers of masks associated with the technological layers involved in parasitic effects; * define (15) in the simplified 3D arrangement a plurality of internal regions, each internal region corresponding to an electronic device of the integrated circuit and an external region corresponding to the part of the simplified 3D arrangement not included in any internal region; * calculate (17, 19) in parallel and independently: * for each internal region, a 3D matrix of adjacent rectangular cuboids, so that there is a boundary between at least two adjacent rectangular cuboids where there is a change of type of doped or where there is a change in the concentration of the doped in the simplified arrangement; * for the external region, a mesh of adjacent rectangular cuboids without overlaps and without spaces; * extract (21) a parasitic component with two terminals between each pair of adjacent cuboids, each terminal being positioned in the center of one of the two adjacent cuboids, so that: * if the two adjacent cuboids have two different types of doped, the parasitic component is defined as a diode; and * if the two adjacent cuboids have the same type of doped with the same doped concentration, the parasitic component is defined as a resistance; and * if the two adjacent cuboids have the same type of doped and different concentrations, the parasitic component is defined as a homounion; and * define (23) the electrical characteristics of each parasitic component based on the geometry of the adjacent cuboids and the technological parameters; and * connect (25) all the parasitic components extracted in an electrical circuit by considering each rectangular cuboid center as a node of the network of parasitic components. characterized in that a set of xyz coordinates is applied on the simplified 3D arrangement, in which the x and y coordinates define horizontal planes and the z coordinate defines the depth of the integrated circuit and the 3D matrix of the internal region is calculated by: * scanning (31) the mask layers to find and collect corner points of change in the type of doped or the concentration of the doped; * flatten (33) the corner points at xy coordinates so that a horizontal rectangular tiling is constructed (35, 37, 39) in which each corner point is a corner of at least one rectangle; * build (43) rectangular cuboid layers by projecting the rectangular tiling on the z axis, the depth of each layer corresponding to the depth of at least one corner point.