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Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit

机译:用于在集成电路中产生电子电路建模基板耦合效应的方法

摘要

Some embodiments are directed to the design and manufacture of integrated circuits, and more particularly, some embodiments are directed to the electrical modeling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, some embodiments are directed to the modeling of substrate coupling effects in these circuits.
机译:一些实施例涉及集成电路的设计和制造,更具体地,一些实施例涉及集成电路的电气建模,其组合具有低电压控制逻辑块的高压功率器件,甚至更具体地说,一些实施例是针对的这些电路中基板耦合效应的建模。

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