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Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
Method for generating an electronic circuit modelling substrate coupling effects in an integrated circuit
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机译:用于在集成电路中产生电子电路建模基板耦合效应的方法
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摘要
Some embodiments are directed to the design and manufacture of integrated circuits, and more particularly, some embodiments are directed to the electrical modeling of integrated circuits combining high voltage power devices with low voltage control logic blocks, and even more particularly, some embodiments are directed to the modeling of substrate coupling effects in these circuits.
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