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DRAM semiconductor device having reduced parasitic capacitance between capacitor contacts and bit line structures and method for manufacturing the same
DRAM semiconductor device having reduced parasitic capacitance between capacitor contacts and bit line structures and method for manufacturing the same
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机译:在电容器触点和位线结构之间具有减小的寄生电容的dram半导体器件及其制造方法
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摘要
A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
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