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DRAM semiconductor device having reduced parasitic capacitance between capacitor contacts and bit line structures and method for manufacturing the same

机译:在电容器触点和位线结构之间具有减小的寄生电容的dram半导体器件及其制造方法

摘要

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.
机译:提供一种半导体器件及其制造方法。该方法包括在半导体衬底上形成多个位线结构,其中在位线结构之间存在多个沟槽。该方法还包括:形成共形地覆盖位线结构和沟槽的第一氧化物层;以及在沟槽中和第一氧化物层上形成光致抗蚀剂材料层,其中,光致抗蚀剂材料层的蚀刻选择性高于光致抗蚀剂材料的蚀刻选择性。第一氧化物层。该方法还包括去除光致抗蚀剂材料层以在位线结构之间形成多个电容器接触孔,以及在电容器接触孔中形成电容器接触。

著录项

  • 公开/公告号US10797057B2

    专利类型

  • 公开/公告日2020-10-06

    原文格式PDF

  • 申请/专利权人 WINBOND ELECTRONICS CORP.;

    申请/专利号US201816183506

  • 发明设计人 WEI-CHE CHANG;TZU-MING OU YANG;

    申请日2018-11-07

  • 分类号H01L27/108;H01L21/033;

  • 国家 US

  • 入库时间 2022-08-21 11:27:51

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